1. Field of the Invention
The present invention relates to a semiconductor device and a semiconductor integrated circuit in each of which at least one hetero junction bipolar transistor is formed, and a method for manufacturing such a semiconductor device, and in particular to a semiconductor device, a semiconductor integrated circuit, and a method for manufacturing such a semiconductor device, which are aimed at preventing the trouble of a hetero junction bipolar transistor caused by a surge.
2. Description of the Related Art
A multi-finger type hetero junction bipolar transistor (hereinafter the hetero junction bipolar transistor is referred to as an HBT) has been used for the transmission of portable devices. The multi-finger type HBT is provided with numerous emitter electrodes disposed in parallel with one another, and is made capable of a high power operation by connecting in common these emitter electrodes to one emitter pad. In the case where numerous emitter electrodes are thus provided, junction resistance, wiring resistance, parasitic capacitance, and the like are large, so that the level of electrostatic withstand voltage (surge withstand voltage) does not constitute a matter of concern for using the multi-finger type HBT.
However, when emitter fingers are used for applications such as a low-noise amplifier for reception, a driver, a mixer, or a transmitter, there are fewer emitter fingers, for example, only two or three.
FIG. 1 is a schematic plan view showing the construction of a semiconductor device having the conventional HBT. In the conventional HBT, a collector layer, an emitter layer, and a base layer are epitaxially grown one after another on a semi-insulating substrate.
A plurality of base electrodes is connected to the base layer, and the base electrodes are connected to base wiring 101b via base through holes 101c. A base pad 110a is provided on the base wiring 101b. Similarly, collector electrodes are connected to the collector layer, and the collector electrodes are connected to collector wiring 102b via collector through holes 102c. A collector pad 102a is provided on the collector wiring 102b. Emitter electrodes are formed to the emitter layer, and the emitter electrodes are connected to emitter wiring 103b via emitter through holes. Emitter pads 103a are provided on both ends of the emitter wiring 103b. 
FIG. 2 is an equivalent circuit showing the construction of a semiconductor device having the conventional HBT. FIG. 2 corresponds to the semiconductor device shown in FIG. 1, apart from the number of transistors. The semiconductor device having the construction as shown in FIG. 1 is equivalent to the circuit having a plurality of HBTs in which, as shown in FIG. 2, each base is connected to a base electrode 111, in which each collector is connected in common to a collector electrode 112, and in which each emitter is connected to an emitter electrode 113.
However, when the number of emitter fingers of an HBT is reduced as described above, junction resistance, wiring resistance, and parasitic capacitance decreases, and thereby a gain is improved, but electrostatic withstand voltage decreases. As a result, the effects of junction capacitance and wiring resistance and the like become less, and consequently the HBT becomes relatively prone to suffer the effect of static electricity. That is, this raises the problem of dropping electrostatic withstand voltage drops, and thereby causing the HBT to be susceptible to a failure. FIG. 3 is a graphical representation showing an emitter current and an inter-terminal voltage at that time. Here, the solid line and the two-dot chain line show the emitter current and the inter-terminal voltage, respectively. FIG. 4 is a diagram showing a circuit used for evaluating the electrostatic withstand voltage.
In measuring the emitter current and the interterminal voltage, there was provided a capacitor 122 of which both electrodes were connected to the collector and the emitter of an HBT 121, respectively, and a power source 123 for charging the capacitor 122 was connected so that the emitter side has a positive potential. A switch 124 for switching between charge and discharge is installed at connection points of the collector and capacitor of the HBT 121, and the negative potential of a power source 123. In the circuit having such a construction, if the capacitor is charged with 20 V voltage and thereafter discharged, an emitter current of about 280 mA instantaneously (in the period of the order of nanoseconds) flows through the HBT 121. Once such a surge arises, in the conventional semiconductor device, the current flows as it is through the HBT, causing the HBT to fail.
The drawback of being low in electrostatic withstand voltage is also found in silicon base bipolar transistors. In order to solve this problem, a proposal has been made of a semiconductor device in which a Zener diode is connected between a collector and a base (Japanese Patent Laid-Open Publication No. Sho 62-244172). Even though such a construction is applied to an HBT, however, it cannot produce a sufficient effect on an HBT of which withstand voltage is low when a positive voltage is applied to its emitter and a negative voltage is applied to its collector.
Another proposal has been made of the semiconductor device using a field-effect transistor of which gate electrode is grounded and which is connected to an output terminal, as a transistor for protecting a surge (Japanese Patent Laid-Open Publication No. Sho 61-216477).
FIG. 5 is a circuit diagram showing the construction of the semiconductor device disclosed in Japanese Patent Laid-Open Publication No. Sho 61-216477. The semiconductor device disclosed in this publication has field-effect transistors 132a and 132b of which gates are connected to input terminals 131a and 131b, respectively. The connection points of the transistors 132a and 132b are connected to an output terminal 134. Also, there is provided a field-effect transistor 133 of which drain is connected between the connection point of the transistors 132a and 132b and the output terminal 134. The gate and the source of the transistor 133 are grounded.
In accordance with this semiconductor device, the intended purpose has been achieved by dispersing a surge voltage by means of the transistor 133. However, the adding of the transistor for protecting surge may deteriorate the performance (gain) of the semiconductor device. The transistor for protecting surge, therefore, cannot be applied to an HBT as it is.
Accordingly, it is an object of the present invention to provide a semiconductor device and a semiconductor integrated circuit, capable of preventing the failure of a hetero junction bipolar transistor caused by a surge, and to provide a method for manufacturing such a semiconductor device.
According to one aspect of the present invention, a semiconductor device comprises a hetero junction bipolar transistor, and a diode connected between a collector and an emitter of the hetero junction bipolar transistor.
The above-mentioned diode may be a hetero junction bipolar transistor whose base and emitter are short-circuited.
Another aspect of the present invention, a semiconductor device comprises a plurality of hetero junction bipolar transistors arranged in a first direction, emitter wiring connected to each emitter of the plural hetero junction bipolar transistors, collector wiring connected to each collector of the plural hetero junction bipolar transistors, and base wiring connected to at least one base of the plural hetero junction bipolar transistors. Bases that are not connected to the base wiring among the bases of the plural hetero junction bipolar transistors are connected to the emitter wiring.
Each of the above-described plurality of hetero junction bipolar transistors may have a base electrode and a collector electrode each of which is arranged like teeth of a comb. The teeth of a comb extend in a second direction orthogonal to the first direction.
According to another aspect of the present invention, a semiconductor device comprises a plurality of hetero junction bipolar transistors arranged in a first direction, at least one diode disposed at predetermined positions between the plural hetero junction bipolar transistors, emitter wiring connected to each emitter of the plural hetero junction bipolar transistors and to an anode of the diode, collector wiring connected to each collector of the plural hetero junction bipolar transistors and to a cathode of the diode, and base wiring connected to each base of the plural hetero junction bipolar transistors.
In the present invention, even if, on occurrence of a surge, a large current tries to flow from the emitter of a hetero junction bipolar transistor to operate as a transistor toward the collector thereof, current generated by the surge hardly flows through the hetero junction bipolar transistor to operate as a transistor, since this current flows through the diode connected between the collector and the emitter of the transistor, or flows between the base and the collector of the hetero junction bipolar transistor whose base is connected to the emitter wiring. This prevents the failure of the hetero junction bipolar transistor to operate as a transistor.
According to another aspect of the present invention, a semiconductor integrated circuit comprises a first hetero junction bipolar transistor, and a second hetero junction bipolar transistor whose base and emitter are connected to an emitter of the first hetero junction bipolar transistor.
According to another aspect of the present invention, a manufacturing method for a semiconductor device comprises forming a first conductive type collector layer on a substrate, forming a plurality of hetero junction bipolar transistors by laminating a plurality of second conductive type base layers and a plurality of first conductive type emitter layers on the collector layer, and forming emitter wiring connected to each of the emitter layers and to a predetermined number of the base layers.
In the manufacturing method of the present invention, since a predetermined number of base layers are connected to the emitter wiring when forming the emitter wiring to be connected to each emitter layer, a hetero junction bipolar transistors whose base and emitter are short-circuited can be easily formed. Furthermore, only by changing the number of base layers connected to the emitter wiring in the above-described step, it is possible for the present method to be adapted to a plurality of types of semiconductor devices. This allows the cost reduction in the development and production of semiconductor device .